Master clock pulse

A master clock pulse is used to coordinate the collection of data on a pixel-by-pixel basis. At each clock pulse, a record is made of the pulses that have been counted by the scaler and the voltages present on analog inputs, and the charge-integration sequence on the segmented silicon detector is restarted.

The source of this master clock pulse varies according to the fast scan axis, as shown in Table 1.2. In the clock interface, Multiplexer 1 has the job of selecting among the following clock inputs used in stepper or spectrum scans (see Secs. 1.2.2 and 7.2):

• Stepping motor pulse inputs for any one of the stages XSTG, YSTG, XDET, or YDET. Pulses corresponding to single motor-step moves of any of these motors motor are obtained by tapping into the internal circuitry of the Newport MM3000 units as described in Sec. 10.2. Pulse logic levels are measured by analog comparators, with a reference voltage derived from the MM3000 units rather than one determined internally on the clock/connect interface board (thus allowing for slight differences in ground voltages between the clock/connect interface board and the MM3000 units).

• The stepping motor pulse input from the monochromator motor controller, labeled as the SGM input. This input is brought through an optoisolator to avoid ground loop problems with the SGM drive electronics.

• Several ALT inputs are provided for future use. These inputs are also brought through optoisolators.

• A 10 kHz fixed clock is also provided to continuously trigger the segmented Si detector when no scans are being done. This is done to avoid charge buildup on the detector's integrating capacitors, and to allow non-streamed analog readouts of the detector signal for flux monitoring purposes.

Three bits (specifying up to $2^{3}=8$ inputs) are provided to Multiplexer 1 by the NI PCI-6503 (a 24 bit digital output board) to select among the above inputs.

The signal selected from the above is then routed into an eight-bit clock divider (the eight divide-by bits are provided by the NI PCI-6503; an additional bit from the NI PCI-6503 is used to reset the divider at the start of scan lines). This divider uses an up-down counter chip to produce one output pulse per every $N$ input pulses ($N=2\ldots 255$), so that one can have pixels of, for example, 1.0 $\mu$m size from motors with an intrinsic step size of 0.1 $\mu$m.

Multiplexer 2 uses two control bits from the NI PCI-6503 to select between three inputs:

• the output of the clock divider described above (on the input labeled ``D'') for a Multiplexer 2 select input of $0=00_{2}$
• the output of Multiplexer 1 which has not been divided (on the input labeled ``1:1'') for a Multiplexer 2 select input of $1=01_{2}$
• a piezo scan trigger pulse (on the input labeled ``P'') for a Multiplexer 2 select input of $2=10_{2}$ or $3=11_{2}$.

This last input is provided from the REQ1 pin of the NI PCI-6534 digital I/O board when it is operated using internal timing to stream out digital output positions in piezo scans. Refer to Secs. 1.2.1 and 7.1 for more information on piezo scan triggering.

The output of Multiplexer 2 is the master clock pulse signal. This signal is routed through line driver chips to provide several externally-available output signals (including one that is used by the segmented silicon detector), and it also provides the trigger signal to the NI PCI-6502E multifunction board used to read analog voltages and count proportional counter pulses (see Sec. 8.3).

In the case of scan modes where external pulses are used as the fast axis clock signal (stepper and spectrum scans; see Table 1.2), the REQ1 pin on the NI PCI-6534 board must serve as a trigger input rather than a pulse output. The clock/connect interface board therefore uses a tri-state buffer as follows:

• If the Multiplexer 2 select input has its high bit set to zero (an input of $0=00_{2}$ or $1=01_{2}$), the Multiplexer 2 pulse output is connected through the tri-state buffer to the NI PCI-6534 REQ1 input as a trigger input pulse.
• If the Multiplexer 2 select input has its high bit set to one (an input of $2=10_{2}$ or $3=11_{2}$), the tri-state output buffer is set to an inactive output state. In this case, the Multiplexer 2 pulse output is not connected to the NI PCI-6534 REQ1 pin, since in this case REQ1 is an output rather than an input.

In this way we avoid the no-no of connecting two logic gate outputs together, even if they are supposed to be at the same output logic level.